1. Field of the Invention
The subject invention relates to a method of forming high resolution electronic circuits on a substrate. In particular, the present invention directs itself to a processing method including the steps of: laminating a substrate with a layer of dielectric film, laser drilling the dielectric film to form a series of channels, filling the channels with an electrically conductive material, applying a release layer to the upper surface of the dielectric film, and removing the release layer, thereby exposing the electrically conductive material formed and patterned on the upper surface of the substrate. More particularly, this invention directs itself to a method of fabricating electronic circuits on a substrate where the laser drilling step allows for the creation of patterns for the electronic circuitry of variable size, shape, and depth on or in the substrate.
2. Prior Art
Methods for forming electronic circuitry on substrates are well-known in the art. In general, such prior art methods include a building process wherein thin layers of dielectric and electrically conductive material are sequentially formed on a base substrate using conventional semiconductor processing techniques. Dielectric layers are typically formed by the sequential steps of spin-coating the dielectric material, curing, pattern-etching with a plasma etch process to form via apertures, and filling the apertures by electroplating or sputtering. The metal layers are typically formed by sequential steps of sputtering a thin chromium layer (for adhesion to the dielectric layer), sputtering an initial copper layer over the chromium layer, defining the electrical traces by either additive or subtractive methods, and removing the excess copper and chromium between the electrical traces.
Typical additive methods use a thin initial copper layer (called a seed layer), then form a photoresist layer over the thin copper layer and pattern it to remove photoresist where the signal traces are to be located, and thereafter plate a much thicker copper layer into the photoresist pattern. Typical subtractive methods use a thick initial copper layer, then form a photoresist layer over the thick copper layer and pattern it in order to remove photoresist in areas where there are signal traces. Thereafter, exposed copper is etched away. The aforementioned building process involves numerous steps and is a relatively expensive procedure. A defect in the formation of one layer may ruin the entire substrate. Current trends in the industry are biased toward increasing the density of signal lines and vias. This, in turn, increases cost of the building process and further increases the chances of a defect occurring.
It is a purpose of the subject invention to provide a method for creating electrical circuitry on a substrate which reduces manufacturing costs and defects and, thusly, enables board manufacturers to keep up with the demands of the semiconductor and circuitry industries.
One such prior art method of forming electrical circuitry on a substrate is shown in U.S. Pat. No. 6,163,957. This reference is directed to a multi-layer laminated substrate with high density interconnects and methods of making the same. The method includes the steps of laminating a substrate with a dielectric material, milling the substrate and dielectric material, and filling the newly formed channels with an electrically conductive substance. The process, however, does not include the steps of baking the electrically conductive material once it has been inserted into the channels, which is necessary for uniformity and strength, nor does it include the step of applying a release layer to remove the unwanted remains of an upper dielectric layer.
Another such prior art method of forming electrical circuitry on a substrate is shown in U.S. Pat. No. 5,576,073. This reference is directed to a method for patterned metallization of a substrate surface. The method includes the steps of laminating a substrate with a dielectric layer, laser drilling channels into the dielectric layer and filling the channels with an electrically conductive substance. The method, however, does not include the steps of baking the electrically conductive material or applying a release layer for removing unwanted remains of an upper dielectric layer.
U.S. Pat. No. 4,710,253 is directed to a method for manufacturing a circuit board. This method includes the steps of layering a conductive powder on a dielectric substrate and irradiating the powder in predetermined shapes and patterns to form permanent circuitry. The method, however, does not include the efficient step of preforming channels in the dielectric layer and then filling them with an electrically conductive material. Nor does it include the step of applying a release layer for removal of unwanted dielectric residue.
U.S. Pat. No. 4,417,393 is directed to a method of fabricating high density electronic circuits having very narrow conductors. This method includes the steps of laser etching channels into a dielectric surface and filling the channels with an electrically conductive material. The electrically conductive material, however, is not baked, nor is it covered with a release layer for removal of unwanted dielectric film.
Another prior art system is shown in U.S. Pat. No. 6,143,356. This reference is directed to a diffusion barrier and adhesive for Parmod application to rigid printing wiring boards. Parmod compositions comprise metal powder mixed with a reactive organic medium, these compositions being applied to temperature-sensitive substrates and cured to well-consolidated, well-bonded circuit traces by beat treatment at a temperature which does not damage the substrate. This system does not include a laser milling and subsequent filling process.
None of the prior art provides for a combination of steps as herein presented comprising a method for forming electronic circuits on a substrate which allows for a maximum of efficiency and cost effectiveness with a minimum of defects. None of the prior art methods include the combined steps of laminating a substrate with a dielectric film, laser milling channels into both the dielectric film and the substrate, filling the channels with an electrically conductive material and subsequently baking the electrically conductive material in order to shape and strengthen the system, and then applying a release layer to adhesively remove the unwanted dielectric film from the top of the substrate.